[Uniquify] Tuyển Junior Physical Design và DFT Engineer Tháng 07/2018


Uniquify Viet Nam One Member LLC
Level 7, Thien Son building, 5 Nguyen Gia Thieu street, ward 6, district 3, HCMC
Level 5, Indochina Riverside Tower building, 74 Bach Dang street, Hai Chau 1 ward, Hai Chau district,
Da Nang city
Work Location: Ho Chi Minh, Da Nang

- Front-to-back SOC design in leading edge technology
- Complex SOC design integration and verification.
- Comprehensive Physical Design from RTL to GDS with in-house PerseusTMDesign Management System
- Design-For-Test and Multiple Corners Static Timing Analysis to enhance the yield and reliability
- Physical verification and power analysis
- Design Automation (CAD) to enable the consistency and predictable tape out schedule and risk mitigation for complex SOC chip.

- In the last year of undergraduate program in Electronics Engineering or Physics Engineering or with working experience of 1-2 years.
- Strong analytical, logical thinking, debugging skills.
- Good understanding of Fundamentals of Synchronous logic design.
- Good communication skills, positive attitude, and ability to work in a team environment.
- High GPA score (7.0 and above)
- A good command of English.
- Exposure to a scripting languages such as TCL, Perl, and/or C-shell is a plus.
- Prefer to working in Linux environment.
- Coursework in digital IC design is a plus.
- Prefer to experiencing with Verilog coding and verification.
- Project or industry experience in ASIC (Backend design: DFT, Layout, STA) is a plus.
- Prefer to understand process window & variation in semiconductor design



Mr. An Huynh, This email address is being protected from spambots. You need JavaScript enabled to view it.